Program > Invited papers

Nanoscale InGaAs Electronics: Lessons towards transistor innovation in new material systems

Jesus del Alamo, MIT, USA

In the last few years, due to its extraordinary electron transport properties, there has been strong interest in the prospects of InGaAs for advanced electronics. Extremely scaled 3D transistors with high aspect-ratio FinFET and nanowire geometries have been demonstrated. Yet, their performance has been disappointing, well below what is to be expected from this material system. This talk will review recent research on nanoscale InGaAs MOSFETs. It will describe some of the technological advances that have been realized at MIT, such as thermal atomic-layer etching and alcohol-based digital etch. It will also describe some of the shortcomings that have been encountered and discuss possible solutions: OFF-state leakage current, mobility degradation in scaled structures and gate oxide trapping. The research holds valuable lessons for the development of advanced electronics on novel material systems.

Prof. del Alamo was an NSF Presidential Young Investigator. He is a member of the Royal Spanish Academy of Engineering and Fellow of the Institute of Electrical and Electronics Engineers, the American Physical Society and the Materials Research Society. He is the recipient of the Intel Outstanding Researcher Award in Emerging Research Devices, the Semiconductor Research Corporation Technical Excellence Award, the IEEE Electron Devices Society Education Award, the University Researcher Award by Semiconductor Industry Association and Semiconductor Research Corporation, the IPRM Award and the IEEE Cledo Brunetti Award. He currently serves as Editor-in-Chief of IEEE Electron Device Letters. He is the author of “Integrated Microelectronic Devices: Physics and Modeling” (Pearson 2017, 880 pages), a rigorous and up to date description of transistors and other contemporary microelectronic devices.

FD-SOI, the path to energy efficiency  for 5G, AI and Automotive applications.

Philippe Flatresse, SOITEC, FRANCE

Fully depleted silicon-on-insulator devices built on an ultrathin SOI layer on a buried-oxide substrate feature unique performance capabilities and are suitable for full-range body biasing. FD-SOI technology has been adopted for multiple technology nodes and a wide range of current and upcoming microelectronic market segments, especially in the Internet of Things (IoT), artificial intelligence (AI), 5G and automotive applications, where ultralow power and reliability are required.

Philippe Flatresse received his PhD degree in Microlectronics in 1999 from the Institut National Polytechnique de Grenoble. During his thesis, he developed the LETISOI spice model dedicated to SOI technologies at CEA LETI. In year 2000, he joined STMicroelectronics Central R&D to deploy the SOI digital design activity. He has pioneered the partially and fully depleted SOI technologies and demonstrated their key advantages for low power high performance digital applications. As design architect, he contributed to the development of products targeting high-growth areas such as ADAS, MCU and IoT applications. He was in charge of exploring the energy efficiency limits on multi-cores systems for ultra-low power processing by combining FD-SOI technology with body biasing, advanced low power techniques. In 2017, he joined SOITEC as expert for digital applications to participate in the worldwide promotion of SOI technologies. He is currently Product Marketing Manager within the FD-SOI business unit.

Runtime Reliability Hardening for Edge AI and Automotive applications

Vincent Huard, DOLPHIN Design, FRANCE

The next decade will see the advent of the Artificial Intelligence both at the edge of the network and in automotive applications. The AI revolution is driven by the need to process the data locally near the sensors to avoid wasting 80% of the overall information available. Such revolution will be enabled by more complex processing architectures located close to the sensors. The new processing architectures imply massively parallel processing which would require expensive margins and/or monitors to insure reliability at the cost of peak performance and energy efficiency. The location close to the sensors implies a greater sensitivity to Process Voltage Temperature (PVT) variations together with Aging variations. The lecture will address what are the solutions foreseen to tackle together the reliability threads and the performance/energy efficiency challenges so to enable the Edge AI revolution. These solutions require to have a 360 degrees approach spanning from technology level (material) through various design stages up to software level.

Vincent Huard received the B.S. (1996) in physics and the M.S. (1997) in electrical engineering from INPG. He received his Ph.D. (2000) in physics from Grenoble university. In 2000, he was Visiting Scholar at UCSB. In 2002, he joined Philips Semiconductors. From 2007 to 2018, he was at STMicroelectronics as Design to Product Reliability manager and a Distinguished Member of Technical Staff. He is now the Chief Technology Officer at Dolphin Design and director of Audio & Processing Product Lines. His research interests cover design for excellence (test, reliability,..), new architectures and toolchains for energy efficient products especially for Edge AI/ML solutions, and new audio solutions. He authored 200+ papers, several invited papers, tutorials and keynotes, held 20+ patents and used to serve as IRPS Management Committee member and in technical committees of various conferences . He is the recipient of the IRPS 2017 and 2018 Best Paper award, the IRPS 2012, 2013, 2016 and 2017 Outstanding Paper awards, the DATE 2015 Best Paper award and the ITC-india 2017 Best Paper award.

AI Techniques for Fault Analysis

Konstantin Schekotihin , AAU Klagenfurt Institute for Applied Informatics, Alpen-Adria-Universität Klagenfurt, AUSTRIA

Identification and localization of faults in semiconductors is a very knowledge-intensive task. The more information an engineer has about a sample at hand, the accurately and cost-effectively its analysis can be done. Often valuable information, such as method know-how, best practices, or reports of previous investigations, is available in different support systems, like file shares, wikis, or databases. However, all these systems are rarely connected since they store information in formats designed for human use only, like unstructured text. As a result, an expert must act as a mediator between such systems by transforming the output of one system into an input format of the other one. Such manual alignment of systems is time-consuming and causes engineers to rely on their own expertise. Modern Artificial Intelligence (AI) methods can help experts to access all required information in a single uniform interface by enabling automated interoperability between the available systems.

In this talk, we discuss logic-based and machine learning methods that can be used to solve the interoperability problem. The first group of methods focuses on applying ontologies to formalize knowledge in the fault analysis domain. The impact of such formalization is twofold. First, ontologies standardize notions used by experts and thus reduce the ambiguity of personal communication. Second, they provide other AI systems with sets of clearly defined concepts and relations between them that machines and experts interpret in the same way. Thus, one can use classes defined in the ontology, e.g., faults, tools, or locations, as labels for training data sets of machine learning methods, such as Natural Language Processing (NLP). The latter can be applied to train classification models that are able to process (un)structured documents from different information systems and align them based on the ontology concepts.

Dr. Konstantin Schekotihin is an associate professor of Intelligent Systems at the University Klagenfurt, Austria, where he leads research and teaching in applications of artificial intelligence methods. He received his MS degree in Informatics from NTU “Kharkow Polytechnic Institute”, Ukraine and his PhD from University Klagenfurt. Dr. Schekotihin research focus lies mainly on various aspects of semantic systems including knowledge representation and reasoning, machine learning for computer vision and natural language processing, knowledge acquisition and maintenance, logic programming and reasoning techniques. Research results were successfully applied in various industrial projects with companies like Infineon or Siemens, focused on topics such as configuration, planning and scheduling, recommendation, or interoperability of systems. He is an author of more than 70 paper in these fields that were published on such prestigious conferences, e.g., IJCAI, ECAI, AAAI, ISWC, or ICDM, and leading international journals as JAIR, IEEE TSE, JWS, or KBS. Dr. Schekotihin is a member of program committees and often acts as a reviewer in a number of international conferences and journals.

Buffer Trap-Induced Current Saturation and Current Collapse in GaN Devices

Michael J. Uren and Martin Kuball, Bristol University, UK

GaN-based HEMTs are now dominant in many high efficiency power amplifier applications, however surprisingly there are many aspects of the devices, especially related to their instabilities that are poorly understood. The semi-insulating buffer layer under the 2D electron gas channel acts to suppress off-state leakage, reduce output conductance and capacitance, but is also the source of multiple issues including current-collapse, dynamic Ron, and kink effect. These are usually discussed in terms of their trap energy levels, cross-sections, and densities. However, here we will show that these instabilities can often be better understood by considering Fermi-level pinning by background carbon acceptors, compensation ratio, and especially the transport to and from the traps dictated by the device electrostatics.

Michael Uren is Research Professor in the Centre for Device Thermography and Reliability at the University of Bristol, UK, and has now accumulated more than 40 years device physics experience. He did his MA and PhD in Physics at the University of Cambridge on electron transport in Si MOSFETs, followed by a postdoc at IBM, Yorktown Heights, USA. He worked at RSRE Malvern, UK (now QinetiQ) on SOI CMOS, random telegraph and 1/f noise, and interface trapping. Later he successfully implemented SiC RF power MESFET, GaN S-band and X-band MMIC processes. He moved to Bristol in 2011 where he leads the device electrical research on GaN, and Ga2O3 devices. His main current interest focuses on the understanding of the role of epitaxy on device performance

State of Health Estimation of Electronic Packages using Piezoresistive Stress sensor

Przemyslaw Gromala, BOSCH, GERMANY

To meet social expectancy, the electronics systems that are used in automotive industry become more complex. The electronic control units that will be used in highly automated and autonomous cars will typically be smart systems of 3rd generation, which will perform human like operations. The 3rd generation smart systems will act independently in respect to control and decision making. In addition, these systems will be capable to self-testing, self-calibration and self-healing. Furthermore, the Internet of Things concept will bring electronic components that are traditionally developed for consumer electronic market under the engine hood.

All of the aforementioned aspects will require new approaches to reliability and quality assurance. It is already observed that the lifetime requirements for embedded electronics used in automotive are increasing. At the same time the time of qualification and the cost of reliability tests are expected to be reduced. All these challenges and requirements can be realized by developing a new reliability concept that is strongly supported through numerical simulation and product optimization at a very early development stage. A possible solution is called prognostics and health managements. I will present an example of in-situ ASIC degradation monitoring of ASIC using a piezoresistive stress sensor. The data driven approach utilizes unique data sets from the stress cells and combines them with the state of health of the IC device. Machine learning techniques are used for fault detection and classification.

Mr Przemyslaw Gromala is a simulation senior expert at Robert Bosch GmbH, Automotive Electronics in Reutlingen. Currently leading an international simulation team and FEM validation and verification lab with the focus on implementation of simulation driven design for electronic control modules and multi-chip power packaging for hybrid drives. His technical expertise includes material characterization and modeling, multi-domain and multi-scale simulation incl. fracture mechanics, V&V techniques, and prognostics and health management for safety relevant electronic smart systems.Prior joining Bosch Mr Gromala worked at Delphi development center in Krakow, as well as at Infineon research and development center in Dresden. He is an active committee member of the IEEE conferences: ECTC, EuroSimE, iTherm; ASME: InterPACK. Active committee member of EPoSS – defining R&D and innovation needs as well as policy requirements related to Smart Systems Integration and integrated Micro- and Nanosystems.He holds a PhD in mechanical engineering from Cracow University of Technology in Poland.

Vertical GaN devices: process and reliability

Shuzhen You, IMEC, BELGIUM

GaN-based power devices have been proven their competence in high power applications. GaN lateral devices are now commercially available rating voltages up to 900V. For higher voltage ratings, the area of lateral HEMTs increase significantly hence degraded cost effectiveness. Additionally, the difficulty in growth of thick buffer layer on Si and poor reliability hinders the development GaN lateral HEMTs. The vertical GaN power devices are promising candidates to realize breakdown voltages >1kV by using thick drift layer without enlarging the device footprint. Moving the peak electric field away from the surface into the bulk minimizes trapping effects and improves device stability and reliability. Vertical GaN diodes and transistors have already been demonstrated, with breakdown voltage up to 4kV. Most of them are grown on free-standing GaN substrates, which is not cost effective for industrial production. Our approach of fabricating the vertical GaN technology on a 200mm CMOS compatible platform, can lead to significant cost savings. This work reviews the challenges related to the substrates, growth of GaN stacks, devices fabrication in 200mm CMOS platform and device performance and reliability.

Shuzhen You, R&D team leader for GaN devices development at imec. She received her master degree in 2003 from East China Normal University in China and her PhD degree in 2012 from KULeuven in Belgium. In 2012, she started her research of GaN power devices in imec. Her research interests include enhancement p-GaN lateral HEMTs and (semi-)vertical MOSFET in device physics, characterization, reliability study and compact modelling. She works on the p-GaN HEMTs devices and compact modelling both for discrete components and monolithically integrated circuits. Since 2019, She has been a work package leader for ECSEL JU project UltimateGaN, working on 200mm CMOS compatible processes for vertical GaN devices targeting a breakdown voltage of 1200V and beyond.

Practical considerations for the reliability of fiber optic monitoring serving condition-based maintenance of aerospace-grade components

Thomas Geernaert, VUB Vrije Universiteit Brussel, BELGIUM

Optical fibre sensors are increasingly used on aerospace-grade carbon fibre reinforced polymer (CFRP) components owing to their light weight, small diameter, multiplexing capabilities and immunity to electromagnetic interference. A permanently installed fiber optic monitoring network of fibre Bragg gratings (FBGs) would allow a transition from time-based maintenance to condition-based maintenance. The current state-of-the-art of BVID detection with OFS remains however at low technology readiness levels and the demonstrations found in literature are often not tested for their compatibility with aerospatial conditions. We therefore address practical considerations for the reliability of fiber optic monitoring: we deploy an in-flight compatible surface mounted OFS network, obtain detection thresholds for BVID detection in view of relevant on-ground conditions, and summarize the health of a component in one Global Damage Index number, based on the readings of the sensor network. We validate our findings on coupon, element and subcomponent level. 

Thomas Geernaert is professor at the Faculty of Engineering of the Vrije Universiteit Brussel. He is member of the Applied Physics and Photonics Department and of the photonics research group B-PHOT (Brussels Photonics), which counts about 70 scientists, engineers, and administrative and technical staff. He graduated as an Electrotechnical Engineer with majors in Photonics in 2006 and received his PhD in Engineering in 2011, both at the VUB. Within B-PHOT, T. Geernaert is leading the research team on optical fiber technologies.

From semiconductor components to the LHC "system of systems": dealing with radiation effects in critical high-energy accelerator equipment

Ruben Garcia Alia, CERN, SWITZERLAND

Successfully operating critical systems based on commercial electronics components in radiation environments poses unique challenges related to the design and qualification of such systems. In this presentation, we will cover the various steps of the Radiation Hardness Assurance (RHA) approach in the Accelerator and Technology Sector (ATS) at CERN, highlighting the key constraints and providing some examples of radiation tolerant developments for accelerators. Such RHA steps include radiation monitoring and calculations in order to specify the related requirements, designing custom systems based on commercial parts and with radiation effects mitigation in mind, as well as the actual radiation qualification of the related semiconductor components and systems.

Rubén García Alía is part of the “Radiation to Electronics” (R2E) project at CERN, which he leads since 2018. After having studied nuclear and high-energy physics in the Complutense University in Madrid (Spain), he started his career in radiation effects as a Young Graturate Trainee at the European Space Agency, in the Netherlands. From there, he moved to completing his PhD with CERN and the University of Montpellier, focusing on the effect of highly energetic particles on Single Event Effects in the LHC accelerator. During this period, he was recognized with the “Best Student Paper” award in RADECS 2012, and the Paul Phelps Award in 2015. Since then, he has kept a strong involvement in radiation effects research with, focusing on high-energy accelerator applications, and has co-authored more than 75 publications in peer reviewed journals. He has also co-authored a RADECS Short Course, has been session chair at NSREC and RADECS, and is currently technical chair for RADECS 2021. Recently he was elected Junior Member-at-Large of the Radiation Effects Steering Group (RESG).

Reliability of automotive and consumer MEMS sensors - an overview

Martina Hommel, BOSCH, GERMANY

In our daily life, sensors play more and more an important role. They take over many functions in the automotive world as well as in consumer products with an increasing dissemination of the internet of things. In addition, they offer a broad variety of new applications. Sensors are typically build up in a package including a sensing element (e.g. micromechanical structures in acceleration sensors or membranes in gas sensors, etc.) and a microelectronic chip to evaluate the sensor data. This article will give an overview, how the reliability of such a system is validated. The challenges for reliability in terms of requirements and qualification for automotive and consumer applications will be discussed. The complex structure of a sensor module in combination with a broad variety of materials implies many possible failure mechanisms, which have to be considered. Some relevant sensor failure mechanisms caused by mechanical shock, thermo-mechanical stress and the influence of humidity on sensor reliability will be shown. The challenges for describing the influence of humidity on the sensor lifetime by an acceleration model will be discussed in detail. Finally, the paper will give an outlook for the reliability challenges of future sensor applications.

Martina Hommel has more than 20 years’ experience in the field of reliability and has worked on several topics including process reliability, power semiconductors and sensors. She has published several papers on reliability, one tutorial about stress migration and holds several patents in this field. She received her diploma in physics (M.S.) in 1996 and her doctoral thesis (Ph.D.) in 1999 on the mechanical properties and fatigue of thin metal films from University of Stuttgart and Max-Planck-Institute for Metals Research (Institute for Material Science), in Stuttgart. In 2000, she joined the Central Reliability Department of Infineon Technologies AG, Munich, where she worked on international technology transfers. The focus of her work was on the reliability of interconnects, inter-metal dielectrics and especially design-for-reliability. Since 2012, she was working for Robert Bosch GmbH, Reutlingen, where she was responsible for the reliability qualification of power semiconductors and power modules for automotive electronics. In 2018, she received as a member of the SiC-development team the Robert Bosch Automotive Electronics Innovation Award. Since 2019, she is working as a Senior Expert for the reliability of sensors, first at Bosch Sensortec GmbH, where she established reliability guidelines and -processes for sensor qualifications of consumer sensors. Now she is a Senior Expert in the sensor development department of automotive sensors.

Innovation and Novelty in Electrostatic Discharge (ESD) and Electrical Overstress from 1980 to 2020

Dr. Steven H. Voldman, ESD Consulting LCC, USA

In this lecture, an overview of the innovation and novelty of electrostatic discharge (ESD) and electrical overstress (EOS) protection from 1980 to 2020 will be discussed. The lecture will review the evolution of design practices, structures, chip architecture, technology, testing models, test equipment, standards, computer aided design (CAD) checking and verification in the ESD protection of semiconductors. The progression of ESD practices in semiconductors, and innovations will be shown. The focus will be on the steps taken to provide improved ESD protection in today’s technologies.

Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.”  Voldman was a member of the semiconductor development of IBM for 25 years. He initiated a lecture series that reached over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, Senegal, Zimbabwe, and China.  Dr. Voldman has teaches short courses and tutorials on ESD, latchup, patenting, and invention.   He is a recipient of 264 issued US patents and has written over 150 technical papers in the area of ESD and CMOS latchup.   Since 2007, he has served as an expert witness in patent litigation; and has also founded a limited liability corporation (LLC) consulting business supporting patents, patent writing and patent litigation